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AS5040
Data Sheet
13 Alignment Mode
The alignment mode simplifies centering the magnet over the chip to gain maximum accuracy and XY-alignment
tolerance.
This electrical centering method allows a wider XY-alignment tolerance (0.485mm radius) than mechanical centering
(0.25mm radius) as it eliminates the placement tolerance of the die within the IC package (+/- 0.235mm).
Alignment mode can be enabled with the falling edge of CSn while Prog = logic high (Figure 18). The Data bits D9-D0
of the SSI change to a 10-bit displacement amplitude output. A high value indicates large X or Y displacement, but
also higher absolute magnetic field strength. The magnet is properly aligned, when the difference between highest
and lowest value over one full turn is at a minimum.
Under normal conditions, a properly aligned magnet will result in a reading of less than 32 over a full turn.
The MagINCn and MagDECn indicators will be = 1 when the alignment mode reading is < 32. At the same time, both
hardware pins MagINCn (#1) and MagDECn (#2) will be pulled to VSS. A properly aligned magnet will therefore
produce a MagINCn = MagDECn = 1 signal throughout a full 360° turn of the magnet.
Stronger magnets or short gaps between magnet and IC may show values larger than 32. These magnets are still
properly aligned as long as the difference between highest and lowest value over one full turn is at a minimum.
The alignment mode can be reset to normal operation mode by a power-on-reset (disconnect / re-connect power
supply).
Figure 18: Enabling the Alignment Mode
Prog
CSn
AlignMode enable
Read-out
via SSI
2μs 2μs
min. min.
14 3.3V / 5V Operation
The AS5040 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-Dropout
(LDO) voltage regulator. The internal supply voltage is always taken from the output of the LDO, meaning that the
internal blocks are always operating at 3.3V.
For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 19).
For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a
2.2...10μF capacitor, which is supposed to be placed close to the supply pin (see Figure 19).
The VDD3V3 output is intended for internal use only It must not be loaded with an external load.
The output voltage of the digital interface I/O’s corresponds to the voltage at pin VDD5V, as the I/O buffers are
supplied from this pin (see Figure 19).
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